A Physical model for gate induced drain leakage current in NMOS transistors at low electrical fields

 

N. Maouhoub, K. Rais*


Laboratoire d’électronique, d’instrumentation et de traitement du signal

Université Chouaib Doukkali, Faculté des sciences B.P 20, EL Jadida, Maroc

* Corresponding author. E-mail: rais_khalid@hotmail.com

Received: 24 February 2011; revised version accepted: 09 July 2011

 

Abstract

      In this work, a physical model for MOSFET gate induced drain leakage current (GIDL) field has proposed witch takes into account of the trap assisted tunneling at low fields and explains a non linearity in Log –Lin Igidl/Fdg2 (1/Fdg) characteristic. The present model is applied on NMOS transistor. We have obtained a good agreement with experimental data.

 

Keywords:  MOS transistor; Tunneling band to band; GIDL; CMOS integrated circuits.


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