STUDY OF THE POWER CONSUMPTION

OF A DIGITAL-FRONT-END USING RANDOM SAMPLING

 

D. Xiaoyu2, M. Diop1*, J.-F. Diouris2

1 Ecole Supérieure Polytechnique, UCAD, BP 5085, Dakar-Fann, Sénégal

2 Ecole polytechnique de l’Université de Nantes, Rue C. Pauc, La Chantrerie,

B.P 50609, 44306, Nantes, cedex 03 – France

* Corresponding author. E-mail: magdiop2002@yahoo.fr, magaye@ucad.sn

Received: 01 July 2013; revised version accepted: 27 April 2014


Abstract

Recently, irregular sampling techniques have been proposed for the design of digital front-end of a radio receiver. This front-end consist in the interface between the analog front-end and the baseband processing. The advantage of these techniques is the simplification of the sampling frequency conversion and the channel selection. The objective of the proposed work is to study if a gain in power consumption is also obtained. In this paper, the major research is the digital-front-end power consumption by using random sampling. Firstly, we introduce the methods of random sampling JRS (Jitter random sampling) and ARS (Additive random sampling). Then we use these methods to generate the random clock, select the hardware as mixed platform with ADC and FPGA and implement different solutions. At last, we measure the power consumption of different solutions and make a comparison.

Keywords: JRS; ARS; FPGA; ADC; Power consumption.

 


 

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